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general description the max5877 is an advanced 14-bit, 250msps, dual digital-to-analog converter (dac). this dac meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. operating from +3.3v and +1.8v supplies, this dual dac offers exceptional dynamic performance such as 75dbc spurious-free dynamic range (sfdr) at f out = 16mhz and supports update rates of 250msps, with a power dissipation of only 287mw.the max5877 utilizes a current-steering architecture that supports a 2ma to 20ma full-scale output current range, and allows a 0.1v p-p to 1v p-p differential output voltage swing. the device features an integrated +1.2vbandgap reference and control amplifier to ensure high-accuracy and low-noise performance. a separate reference input (refio) allows for the use of an exter- nal reference source for optimum flexibility and improved gain accuracy. the clock inputs of the max5877 accept both lvds and lvpecl-compatible voltage levels. the device fea- tures an interleaved data input that allows a single lvds bus to support both dacs. the max5877 is avail- able in a 68-pin qfn package with an exposed pad (ep) and is specified for the extended temperature range (-40? to +85?). refer to the max5876 and max5878 data sheets for pin-compatible 12-bit and 16-bit versions of the max5877, respectively. refer to the max5874 data sheet for a cmos-compatible version of the max5877. applications base stations: single/multicarrier umts, cdma, gsmcommunications: fixed broadband wireless access, point-to-point microwave direct digital synthesis (dds) cable modem termination systems (cmts) automated test equipment (ate) instrumentation features ? 250msps output update rate ? noise spectral density = -160dbfs/hzat f out = 16mhz ? excellent sfdr and imd performance sfdr = 75dbc at f out = 16mhz (to nyquist) sfdr = 71dbc at f out = 80mhz (to nyquist) imd = -87dbc at f out = 10mhz imd = -73dbc at f out = 80mhz ? aclr = 75db at f out = 61mhz ? 2ma to 20ma full-scale output current ? lvds-compatible digital and clock inputs ? on-chip +1.20v bandgap reference ? low 287mw power dissipation ? compact 68-pin qfn-ep package (10mm x 10mm) ? evaluation kit available (max5878evkit) max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs ________________________________________________________________ maxim integrated products 1 pin configuration ordering information 19-3632; rev 2; 3/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad. + = lead-free package. d = dry pack. evaluation kit available part temp range pin- package pkg code MAX5877EGK-D -40? to +85? 68 qfn-ep* g6800-4 max5877egk+d -40? to +85? 68 qfn-ep* g6800-4 selector guide part resolution (bits) update rate (msps) logic inputs max5873 12 200 cmos max5874 14 200 cmos max5875 16 200 cmos max5876 12 250 lvds max5877 14 250 lvds max5878 16 250 lvds 5859606162 54555657 63 38 39 40 41 42 43 44 45 46 47 dv dd3.3 av dd1.8 b5n qfn top view b5pdv dd1.8 b6nb6p b7n b7p b8n b8p b9n 5253 b9p b10n dacref av dd3.3 gnd gnd av dd3.3 outqp outqn gnd gnd outip outin av dd3.3 gnd av dd3.3 b12pb13n b13p seliqn seliqp xorpxorn pd torb clkp 35 36 37 clkn gnd av clk gnd n.c. n.c. n.c. n.c. refio gnd av dd3.3 gnd gnd b0n b0p b1n b1p 48 b12n b2n 64 b4p 656667 b3nb3p b4n 68 b2p 2322212019 27262524 18 2928 323130 gnd av dd1.8 3433 49 50 b11nb11p 51 b10p 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 fsadj 17 max5877 downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd1.8 , dv dd1.8 to gnd, dacref...................-0.3v to +2.16v av dd3.3 , dv dd3.3 , av clk to gnd, dacref ........-0.3v to +3.9v refio, fsadj to gnd, dacref..................................-0.3v to (av dd3.3 + 0.3v) outip, outin, outqp, outqn to gnd, dacref...................-1v to (av dd3.3 + 0.3v) clkp, clkn to gnd, dacref..............-0.3v to (av clk + 0.3v) b13p/b13n?0p/b0n, xorn, xorp, seliqn, seliqp to g nd, dacref ...................-0.3v to (dv dd1.8 + 0.3v) torb, pd to gnd, dacref ...............-0.3v to (dv dd3.3 + 0.3v) continuous power dissipation (t a = +70?) 68-pin qfn-ep (derate 41.7mw/? above +70?) (note 1) ............3333.3mw thermal resistance ja (note 1)...................................+24?/w operating temperature range ......................... -40? to +85? junction temperature .................................................... +150? storage temperature range ........................... -60? to +150? lead temperature (soldering, 10s) ............................... +300? parameter symbol conditions min typ max units static performance resolution 14 bits integral nonlinearity inl measured differentially 0.5 lsb differential nonlinearity dnl measured differentially 0.2 lsb offset error os -0.025 0.001 +0.025 %fs offset-drift tempco 10 ppm/ c full-scale gain error ge fs external reference -4.6 -0.6 +4.6 %fs internal reference 100 gain-drift tempco external reference 50 ppm/ c full-scale output current i outfs (note 3) 2 20 ma output compliance single-ended -0.5 +1.1 v output resistance r out 1m ? output capacitance c out 5p f dynamic performance clock frequency f clk 2 500 mhz output update rate f dac f dac = f clk / 2 1 250 msps f dac = 150mhz f out = 16mhz, -12dbfs -160 noise spectral density f dac = 250mhz f out = 80mhz, -12dbfs -157 dbfs/ hz electrical characteristics(av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, gnd = 0, f clk = 2 x f dac , external reference v refio = +1.25v, out- put load 50 ? double-terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) note 1: thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area. downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs _______________________________________________________________________________________ 3 electrical characteristics (continued)(av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, gnd = 0, f clk = 2 x f dac , external reference v refio = +1.25v, out- put load 50 ? double-terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units f out = 1mhz, 0dbfs 98 f out = 1mhz, -6dbfs 86 f out = 1mhz, -12dbfs 78 f out = 10mhz, -12dbfs 77 f dac = 100mhz f out = 30mhz, -12dbfs 78 f out = 10mhz, -12dbfs 75 f out = 16mhz, -12dbfs 66 75 f out = 50mhz, -12dbfs 74 f dac = 200mhz f out = 80mhz, -12dbfs 71 f out = 10mhz, -12dbfs 74 f out = 50mhz, -12dbfs 72 f out = 80mhz, -12dbfs 71 spurious-free dynamic rangeto nyquist sfdr f dac = 250mhz f out = 100mhz, -12dbfs 68 dbc spurious-free dynamic range,25mhz bandwidth sfdr f dac = 150mhz f out = 16mhz, -12dbfs 80 dbc f dac = 100mhz f out1 = 9mhz, -7dbfs; f out2 = 10mhz, -7dbfs -87 two-tone imd ttimd f dac = 200mhz f out1 = 79mhz, -7dbfs; f out2 = 80mhz, -7dbfs -73 dbc four-tone imd, 1mhz frequency spacing, gsm model ftimd f dac = 150mhz f out = 16mhz, -12dbfs -94 dbc adjacent channel leakage powerratio 3.84mhz bandwidth, w-cdma model aclr f dac = 184.32mhz f out = 61.44mhz 75 db output bandwidth bw -1db (note 4) 240 mhz inter-dac characteristics f out = dc - 80mhz 0.2 gain matching ? gain f out = dc -0.25 +0.01 +0.25 db gain-matching tempco ? gain/ c 20 ppm/ c phase matching ? phase f out = 60mhz 0.25 d egr ees phase-matching tempco ? phase/ c f out = 60mhz 0.002 d eg r ees/ c channel-to-channel crosstalk f dac = 200msps, f out = 50mhz, 0dbfs 90 db reference internal reference voltage range v refio 1.14 1.2 1.26 v downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 4 _______________________________________________________________________________________ electrical characteristics (continued)(av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, gnd = 0, f clk = 2 x f dac , external reference v refio = +1.25v, out- put load 50 ? double-terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units reference input compliancerange v refiocr 0.125 1.260 v reference input resistance r refio 10 k reference voltage drift tco ref 25 ppm/ c analog output timing (see figure 4) output fall time t fall 90% to 10% (note 5) 0.7 ns output rise time t rise 10% to 90% (note 5) 0.7 ns output-voltage settling time t settle output settles to 0.025% fs (note 5) 14 ns output propagation delay t pd excluding data latency (note 5) 1.1 ns glitch impulse measured differentially 1 pv s i outfs = 2ma 30 output noise n out i outfs = 20ma 30 pa/ hz timing characteristics data to clock setup time t setup referenced to rising edge of clock (note 6) -1.2 ns data to clock hold time t hold referenced to rising edge of clock (note 6) 2.0 ns latency to i output 9 data latency latency to q output 8 clock cycles minimum clock pulse-width high t ch clkp, clkn 0.9 ns minimum clock pulse-width low t cl clkp, clkn 0.9 ns lvds logic inputs (b13p/b13n?0p/b0n, xorn, xorp, seliqn, seliqp) differential input-logic high v ih 100 mv differential input-logic low v il -100 mv common-mode voltage range v cmr 1.125 1.375 v differential input resistance r in (note 7) 110 input capacitance c in 2.5 pf cmos logic inputs (pd, torb) input-logic high v ih 0.7 x dv dd3.3 v input-logic low v il 0.3 x dv dd3.3 v input leakage current i in -20 1 +20 ? pd, torb internal pulldown resistance v pd = v torb = 3.3v 1.5 m input capacitance c in 2.5 pf clock inputs (clkp, clkn) sine wave > 1.5 differential inputvoltage swing square wave > 0.5 v p-p downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs _______________________________________________________________________________________ 5 electrical characteristics (continued)(av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, gnd = 0, f clk = 2 x f dac , external reference v refio = +1.25v, out- put load 50 ? double-terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) note 2: specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design. note 3: nominal full-scale current i outfs = 32 x i ref . note 4: this parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the max5877. note 5: parameter measured single-ended into a 50 ? termination resistor. note 6: not production tested. guaranteed by design. note 7: no termination resistance between xorp and xorn. note 8: a differential clock input slew rate of > 100v/? is required to achieve the specified dynamic performance. note 9: parameter defined as the change in midscale output caused by a ?% variation in the nominal supply voltage. parameter symbol conditions min typ max units differential input slew rate sr clk (note 8) >100 v/? external common-mode voltagerange v com av clk / 2 0.3 v input resistance r clk 5k ? input capacitance c clk 2.5 pf power supplies av dd3.3 3.135 3.3 3.465 analog supply voltage range av dd1.8 1.710 1.8 1.890 v dv dd3.3 3.135 3.3 3.465 digital supply voltage range dv dd1.8 1.710 1.8 1.890 v clock supply voltage range av clk 3.135 3.3 3.465 v f dac = 250msps, f out = 16mhz 52 58 ma i avdd3.3 + i avclk power-down 1 a f dac = 250msps, f out = 16mhz 30 36 ma analog supply current i avdd1.8 power-down 1 a f dac = 250msps, f out = 16mhz 0.2 1 ma i dvdd3.3 power-down 1 a f dac = 250msps, f out = 16mhz 34 40 ma digital supply current i dvdd1.8 power-down 4 a f dac = 250msps, f out = 16mhz 287 331 mw power dissipation p diss power-down 16 ? power-supply rejection ratio psrr av dd3.3 = av clk = dv dd3.3 = +3.3v 5% (notes 8, 9) -0.1 +0.1 %fs/v downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 6 _______________________________________________________________________________________ single-tone sfdr vs. output frequency (f dac = 50msps) max5877 toc01 f out (mhz) sfdr (dbc) 20 15 10 5 20 40 60 80 100 0 02 5 -12dbfs -6dbfs 0dbfs single-tone sfdr vs. output frequency (f dac = 100msps) max5877 toc02 f out (mhz) sfdr (dbc) 40 30 20 10 20 40 60 80 100 0 05 0 -12dbfs -6dbfs 0dbfs single-tone sfdr vs. output frequency (f dac = 150msps) max5877 toc03 f out (mhz) sfdr (dbc) 60 45 30 15 20 40 60 80 100 0 07 5 -12dbfs -6dbfs 0dbfs t ypical operating characteristics (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference, v refio = +1.25v, r l = 50 ? double-terminated, i outfs = 20ma, t a = +25?, unless otherwise noted.) single-tone sfdr vs. output frequency (f dac = 200msps) max5877 toc04 f out (mhz) sfdr (dbc) 80 60 40 20 20 40 60 80 100 0 01 0 0 -12dbfs -6dbfs 0dbfs single-tone sfdr vs. output frequency (f dac = 250msps) max5877 toc05 f out (mhz) sfdr (dbc) 100 75 50 25 20 40 60 80 100 0 01 2 5 -12dbfs -6dbfs 0dbfs two-tone imd vs. output frequency (1mhz carrier spacing, f dac = 100msps) max5877 toc06 f out (mhz) two-tone imd (dbc) 35 30 25 20 15 10 -90 -85 -100 -80-95 54 0 -12dbfs -6dbfs downloaded from: http:///
two-tone intermodulation distortion (f dac = 100msps) max5877 toc07 f out (mhz) output power (dbfs) 34 32 30 28 26 -80 -60 -40 -20 0 -100 24 36 bw = 12mhz 2 x f t1 - f t2 2 x f t2 - f t1 f t1 f t2 f t1 = 28.9795mhz f t2 = 30.0049mhz two-tone imd vs. output frequency (1mhz carrier spacing, f dac = 200msps) max5877 toc08 f out (mhz) two-tone imd (dbc) 70 60 50 40 30 20 10 -95 -90 -85 -80 -75 -70 -65 -60 -100 08 0 -12dbfs -6dbfs sfdr vs. full-scale output current (f dac = 250msps) max5877 toc09 f out (mhz) sfdr (dbc) 100 75 50 25 20 40 60 80 100 0 01 2 5 a out = -6dbfs 10ma 5ma 20ma sfdr vs. temperature (f dac = 250msps) max5877 toc10 f out (mhz) sfdr (dbc) 100 75 50 25 75 80 85 9070 01 2 5 a out = -6dbfs t a = +85 c t a = +25 c t a = -40 c integral nonlinearity vs. digital input code max5877 toc11 digital input code inl (lsb) 12,288 8192 4096 -0.5 0 0.5 1.0 0 16,384 -1.0 differential nonlinearity vs. digital input code max5877 toc12 digital input code dnl (lsb) 12,288 8192 4096 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.4 01 6 ,384 max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs _______________________________________________________________________________________ 7 t ypical operating characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference, v refio = +1.25v, r l = 50 ? double-terminated, i outfs = 20ma, t a = +25?, unless otherwise noted.) downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = +3.3v, av dd1.8 = dv dd1.8 = +1.8v, external reference, v refio = +1.25v, r l = 50 ? double-terminated, i outfs = 20ma, t a = +25?, unless otherwise noted.) power dissipation vs. dac update rate (f out = 10mhz) max5877 toc13 f dac (msps) power dissipation (mw) 200 250 150 100 50 200 220 240 280 260 300180 0 a out = 0dbfs power dissipation vs. supply voltage (f dac = 100msps, f out = 10mhz) max5877 toc14 supply voltage (v) power dissipation (mw) 3.465 3.300 210 220 225205 3.135 a out = 0dbfs external reference internal reference 215 four-tone power ratio plot (f dac = 150mhz) max5877 toc15 f out (mhz) output power (dbfs) 36 34 32 30 28 -80 -60 -40 -20 0 -100 26 38 bw = 12mhz f t1 f t2 f t3 f t4 f t1 = 29.6997mhz f t2 = 30.7251mhz f t3 = 31.6040mhz f t4 = 32.4829mhz aclr for wcdma modulation, single-carrier aclr max5877 toc16 9.216mhz/div analog output power (dbm) -110 -100 -90 -80 -70 -60 -50 -40 -30 1mhz 92.16mhz f dac = 184.32mbps f carrier = 30.72mhz aclr = +80db -20 aclr for wcdma modulation two-carrier aclr max5877 toc17 3.05mhz/div analog output power (dbm) -110 -120 -100 -90 -80 -70 -60 -50 -40 -30 f dac = 245.76msps f center = 30.72mhz aclr = +77db aclr for wcdma modulation two-carrier aclr max5877 toc18 3.05mhz/div analog output power (dbm) -110 -100 -90 -80 -70 -60 -50 -30 -120 f dac = 184.32msps f center = 30.72mhz aclr = +77db -40 wcdma baseband aclr (f dac = 245.76msps) max5877 toc19 number of channels aclr (db) 4 3 2 1 76 77 79 81 8275 81.4 80.2 80.9 79.5 79.5 78.9 77.2 77.2 alternate adjacent 78 80 79.0 downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs _______________________________________________________________________________________ 9 pin description pin name function 1 b2n complementary data bit 2 2 b1p data bit 1 3 b1n complementary data bit 1 4 b0p data bit 0 (lsb) 5 b0n complementary data bit 0 (lsb) 6? n.c. no connection. leave floating or connect to gnd. 10, 12, 13, 15,20, 23, 26, 27, 30, 33, 36 gnd ground 11 dv dd3.3 digital supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1?capacitor to gnd. 14, 21, 22, 31, 32 av dd3.3 analog supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass each pin witha 0.1? capacitor to gnd. 16 refio reference i/o. output of the internal 1.2v precision bandgap reference. bypass with a 1? capacitor to gnd. refio can be driven with an external reference source. see table 1. 17 fsadj full-scale adjust input. this input sets the full-scale output current of the dac. for a 20ma full-scale output current, connect a 2k resistor between fsadj and dacref. see table 1. 18 dacref current-set resistor return path. internally connected to gnd. do not use as an external ground connection. 19, 34 av dd1.8 analog supply voltage. accepts a 1.71v to 1.89v supply voltage range. bypass each pin with a0.1? capacitor to gnd. 24 outqn complementary q-dac output. negative terminal for current output. 25 outqp q-dac output. positive terminal for current output. 28 outin complementary i-dac output. negative terminal for current output. 29 outip i-dac output. positive terminal for current output. 35 av clk clock supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1?capacitor to gnd. 37 clkn complementary converter clock input. negative input terminal for lvds/lvpecl-compatibledifferential converter clock. internally biased to av clk / 2. 38 clkp converter clock input. positive input terminal for lvds/lvpecl-compatible differential converterclock. internally biased to av clk / 2. 39 torb two?-complement/binary select input. set torb to a cmos-logic-high level to indicate a two?-complement input format. set torb to a cmos-logic-low level to indicate an offset binary input format. torb has an internal pulldown resistor. downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 10 ______________________________________________________________________________________ pin description (continued) pin name function 40 pd power-down input. set pd to a cmos-logic-high level to force the dac into power-down mode.set pd to a cmos-logic-low level for normal operation. pd has an internal pulldown resistor. 41 xorn complementary lvds dac exclusive-or select input. set xorn high and xorp low to allowthe data stream to pass unchanged to the dac input. set xorn low and xorp high to invert the dac input data. if unused, connect xorn to dv dd1.8 . 42 xorp lvds dac exclusive-or select input. set xorn high and xorp low to allow the data stream topass unchanged to the dac input. set xorn low and xorp high to invert the dac input data. if unused, connect xorp to gnd. 43 seliqp lvds dac select input. set seliqn low and seliqp high to direct data to the i-dac outputs.set seliqp low and seliqn high to direct data to the q-dac outputs. 44 seliqn complementary lvds dac select input. set seliqn low and seliqp high to direct data to thei-dac outputs. set seliqp low and seliqn high to direct data to the q-dac outputs. 45 b13p data bit 13 (msb) 46 b13n complementary data bit 13 (msb) 47 b12p data bit 12 48 b12n complementary data bit 12 49 b11p data bit 11 50 b11n complementary data bit 11 51 b10p data bit 10 52 b10n complementary data bit 10 53 b9p data bit 9 54 b9n complementary data bit 9 55 b8p data bit 8 56 b8n complementary data bit 8 57 b7p data bit 7 58 b7n complementary data bit 7 59 b6p data bit 6 60 b6n complementary data bit 6 61 dv dd1.8 digital supply voltage. accepts a 1.71v to 1.89v supply voltage range. bypass with a 0.1?capacitor to gnd. 62 b5p data bit 5 63 b5n complementary data bit 5 64 b4p data bit 4 65 b4n complementary data bit 4 66 b3p data bit 3 67 b3n complementary data bit 3 68 b2p data bit 2 ? p exposed pad. must be connected to gnd through a low-impedance path. downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs ______________________________________________________________________________________ 11 latch xor/ decode latch lvds receiver latch latch dac outip outin latch xor/ decode latch latch dac outqp outqn fsadj torb seliqn xorp xorn av clk clkn clkp clk interface data13 d ata0 +1.2v reference power-down block refio dacref pd gnd dv dd1.8 dv dd3.3 av dd1.8 av dd3.3 seliqp max5877 figure 1. max5877 high-performance, 14-bit, dual current-steering dac detailed description architecture the max5877 high-performance, 14-bit, dual current-steering dac (figure 1) operates with dac update rates up to 250msps. the converter consists of input registers and a demultiplexer for single-port operation, followed by a current-steering array. during operation, the input data registers demultiplex the single-port data bus. the cur- rent-steering array generates differential full-scale cur- rents in the 2ma to 20ma range. an internal current-switching network, in combination with external 50 ? termination resistors, converts the differential output currents into dual differential output voltages with a 0.1vto 1v peak-to-peak output voltage range. an integrated +1.2v bandgap reference, control amplifier, and user- selectable external resistor determine the data convert- er? full-scale output range. reference architecture and operation the max5877 supports operation with the internal+1.2v bandgap reference or an external reference volt- age source. refio serves as the input for an external, low-impedance reference source. refio also serves as a reference output when the dac operates in internal reference mode. for stable operation with the internal reference, decouple refio to gnd with a 1? capaci- tor. due to its limited output drive capability, buffer refio with an external amplifier when driving large external loads. downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 12 ______________________________________________________________________________________ the max5877? reference circuit (figure 2) employs acontrol amplifier to regulate the full-scale current i outfs for the differential current outputs of the dac. calculate the full-scale output current as follows:where i outfs is the full-scale output current of the dac. r set (located between fsadj and dacref) determines the amplifier? full-scale output current forthe dac. see table 1 for a matrix of different i outfs and r set selections. analog outputs (outip, outin, outqp, outqn) each max5877 dac outputs two complementary cur-rents (outip/n, outqp/n) that operate in a single- ended or differential configuration. a load resistor converts these two output currents into complementary single-ended output voltages. a transformer or a differ- ential amplifier configuration converts the differential voltage existing between outip (outqp) and outin (outqn) to a single-ended voltage. if not using a transformer, the recommended termination from the output is a 25 ? termination resistor to ground and a 50 ? resistor between the outputs. to generate a single-ended output, select outip (oroutqp) as the output and connect outin (or outqn) to gnd. sfdr degrades with single-ended operation or increased output swing. figure 3 displays a simpli- fied diagram of the internal output structure of the max5877. clock inputs (clkp, clkn) the max5877 features flexible differential clock inputs(clkp, clkn) operating from a separate supply (av clk ) to achieve optimum jitter performance. drive the differential clock inputs from a single-ended or adifferential clock source. for single-ended operation, drive clkp with a logic source and bypass clkn to gnd with a 0.1? capacitor. clkp and clkn are internally biased to av clk / 2. this facilitates the ac-coupling of clock sources directly tothe device without external resistors to define the dc level. the dynamic input resistance from clkp and clkn to ground is 5k ? . i v r outfs refio set = ? ? ? ? ? ? 32 1 1 2 14 table 1. i outfs and r set selection matrix based on a typical +1.200vreference voltage r set (k ? ) full-scale current i outfs (ma) calculated 1% eia std 2 19.2 19.1 5 7.68 7.5 10 3.84 3.83 15 2.56 2.55 20 1.92 1.91 outip outin +1.2v reference current-source array dac refiofsadj r set i ref 10k ? dacref 1 f i ref = v refio / r set gnd figure 2. reference architecture, internal referenceconfiguration i out i out outin outip current sources current switches av dd figure 3. simplified analog output structure downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs ______________________________________________________________________________________ 13 seliqp clkp-clkn d ata in i0 q2 i2 q1 i1 i3 q3 q0 t s t h outi outq t pd i0 - 5 i0 - 4 i0 - 2 i0 - 3 i0 - 6 q0 - 6 q0 - 5 q0 - 4 q0 - 3 q0 - 2 seliqn figure 4. timing diagram data timing relationship figure 4 displays the timing relationship between digitallvds data, clock, and output signals. the max5877 features a 2.0ns hold, a -1.2ns setup, and a 1.1ns prop- agation delay time. a nine (eight)-clock-cycle latency exists between clkp/clkn and outip/outin (outqp/outqn). lvds-compatible digital inputs (b13p/b13n?0p/b0n, xorp, xorn, seliqp, seliqn) the max5877 latches b13p/n?0p/n, xorp/n, andseliqp/n data on the rising edge of the clock. a logic- high signal on seliqp and a logic-low signal on seliqn directs data onto the i-dac inputs. a logic-low signal on seliqp and a logic-high signal on seliqn directs data onto the q-dac inputs. the max5877 features lvds receivers on the bus input interface with internal 110 ? termination resistors. see figure 5. xorp and xorn are not internally terminated. these lvds inputs (b13p/n?0p/n) allow for a low differ- ential voltage swing with low constant power consump- tion. a 1.25v common-mode level and 250mv differential input swing can be applied to the b13p/n?0p/n, xorp/n, and seliqp/n inputs. the max5877 includes lvds-compatible exclusive-or inputs (xorp, xorn). input data (all bits) is compared with the bits applied to xorp and xorn through exclu- sive-or gates. setting xorp high and xorn low inverts the input data. setting xorp low and xorn high leaves the input data noninverted. by applying a previously encoded pseudo-random bit stream to the data input and applying decoding to xorp/xorn, the digital input data can be decorrelated from the dac output, allowing for the troubleshooting of possible spurious or harmonic distortion degradation due to digital feedthrough on the printed circuit board (pcb). if xor functionality is not required, connect xorp to gnd and xorn to dv dd1.8 . downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 14 ______________________________________________________________________________________ cmos-compatible digital inputs input data format select (torb) the torb input selects between two?-complement oroffset binary digital input data. set torb to a cmos- logic-high level to indicate a two?-complement input format. set torb to a cmos-logic-low level to indicate an offset binary input format. power-down operation (pd) the max5877 also features an active-high power-downmode that reduces the dac? digital current consump- tion from 34ma to less than 5? and the analog current consumption from 82ma to less than 2?. set pd high to power down the max5877. set pd low for normal operation. when powered down, the max5877 reduces the overall power consumption to less than 16?. the max5877 requires 10ms to wake up from power-down and enter a fully operational state. the pd integrated pulldown resistor activates the max5877 if pd is left floating. applications information clk interface the max5877 features a flexible differential clock input(clkp, clkn) with a separate supply (av clk ) to achieve optimum jitter performance. use an ultra-lowjitter clock to achieve the required noise density. clock jitter must be less than 0.5ps rms for meeting the speci- fied noise density. for that reason, the clkp/clkninput source must be designed carefully. the differen- tial clock (clkn and clkp) input can be driven from a single-ended or a differential clock source. differential clock drive is required to achieve the best dynamic performance from the dac. for single-ended opera- tion, drive clkp with a low noise source and bypass clkn to gnd with a 0.1? capacitor. figure 6 shows a convenient and quick way to apply a differential signal created from a single-ended source (e.g., hp 8662a signal generator) and a wideband trans- former. alternatively, these inputs can be driven from a cmos-compatible clock source; however, it is recom- mended to use sinewave or ac-coupled differential ecl/pecl or lvds drive for best dynamic performance. 110 ? todecode logic dd qq b13p?0p, seliqp b13n?0n, seliqn clock max5877 figure 5. simplified lvds-compatible digital input structure digital input code offset binary two? complement out_p out_n 00 0000 0000 0000 10 0000 0000 0000 0 i outfs 01 1111 1111 1111 00 0000 0000 0000 i outfs / 2 i outfs / 2 11 1111 1111 1111 01 1111 1111 1111 i outfs 0 table 2. dac output code table wideband rf transformer performs single-ended-to- differential conversion single-ended clock source (e.g., hp 8662a) gnd 1:1 25 ? 25 ? clkpclkn to dac 0.1 f 0.1 f figure 6. differential clock-signal generation downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs ______________________________________________________________________________________ 15 differential-to-single-ended conversion using a wideband rf transformer use a pair of transformers (figure 7) or a differentialamplifier configuration to convert the differential voltage existing between outip/outqp and outin/outqn to a single-ended voltage. optimize the dynamic perfor- mance by using a differential transformer-coupled out- put and limit the output power to < 0dbm full scale. pay close attention to the transformer core saturation char- acteristics when selecting a transformer for the max5877. transformer core saturation can introduce strong 2nd-order harmonic distortion especially at low output frequencies and high signal amplitudes. for best results, center tap the transformer to ground. when not using a transformer, terminate each dac output to ground with a 25 ? resistor. additionally, place a 50 ? resistor between the outputs (figure 8).for a single-ended unipolar output, select outip (outqp) as the output and ground outin (outqn). driving the max5877 single-ended is not recommend- ed since additional noise and distortion will be added. the distortion performance of the dac depends on the load impedance. the max5877 is optimized for 50 ? differential double termination. it can be used with atransformer output as shown in figure 7 or just one 25 ? resistor from each output to ground and one 50 ? resis- tor between the outputs (figure 8). this produces a full-scale output power of up to -2dbm, depending on the output current setting. higher termination impedance can be used at the cost of degraded distortion perfor- mance and increased output noise voltage. grounding, bypassing, and power- supply considerations grounding and power-supply decoupling can stronglyinfluence the max5877 performance. unwanted digital crosstalk couples through the input, reference, power supply, and ground connections, and affects dynamic performance. high-speed, high-frequency applications require closely followed proper grounding and power- supply decoupling. these techniques reduce emi and internal crosstalk that can significantly affect the max5877 dynamic performance. use a multilayer pcb with separate ground and power- supply planes. run high-speed signals on lines directly above the ground plane. keep digital signals as far away from sensitive analog inputs and outputs, reference input sense lines, and clock inputs as practical. use a con- trolled-impedance, symmetric, differential design of data input, clock input, and the analog output lines to minimize 2nd-order harmonic distortion and noise components, thus optimizing the dac? dynamic performance. keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. the max5877 requires five separate power-supply inputs for analog (av dd1.8 and av dd3.3 ), digital (dv dd1.8 and dv dd3.3 ), and clock (av clk ) circuitry. all power-supply pins must be connected to their proper supply. decoupleeach av dd , dv dd , and av clk input pin with a separate 0.1? capacitor as close to the device as possible withthe shortest possible connection to the ground plane (figure 9). minimize the analog and digital load capaci- tances for optimized operation. decouple all three power-supply voltages at the point they enter the pcb with tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. max5877 14 outip/outqpoutin/outqn data13?ata0 wideband rf transformer t2 performs thedifferential-to-single-ended conversion t1, 1:1 t2, 1:1 gnd 50 ? 100 ? 50 ? v out , single-ended figure 7. differential-to-single-ended conversion using a wideband rf transformer downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 16 ______________________________________________________________________________________ the analog and digital power-supply inputs av dd3.3 , av clk , and dv dd3.3 allow a +3.135v to +3.465v sup- ply voltage range. the analog and digital power-supplyinputs av dd1.8 and dv dd1.8 allow a +1.71v to +1.89v supply voltage range. the max5877 is packaged in a 68-pin qfn-ep pack- age, providing greater design flexibility and optimized dac ac performance. the ep enables the use of nec- essary grounding techniques to ensure highest perfor- mance operation. thermal efficiency is not the key factor, since the max5877 features low-power opera- tion. the exposed pad ensures a minimum inductance ground connection between the dac and the pcb? ground layer. the data converter die attaches to an ep lead frame with the back of this frame exposed at the package bot- tom surface, facing the pcb side of the package. this allows for a solid attachment of the package to the pcb with standard infrared reflow (ir) soldering techniques. a specially created land pattern on the pcb, matching the size of the ep (6mm x 6mm), ensures the proper attachment and grounding of the dac (refer to the max5878 ev kit). designing vias into the land area and implementing large ground planes in the pcb design allow for the highest performance operation of the dac. use an array of at least 4 x 4 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) for this68-pin qfn-ep package. connect the max5877 exposed paddle to gnd. vias connect the land pattern to internal or external copper planes to spread heat. use as many vias as possible to the ground plane to mini- mize inductance. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actu- al step height and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees a monotonic transfer function. offset error the offset error is the difference between the ideal andthe actual offset current. for a dac, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the dac. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and theactual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same per cent- age error in each step. max5877 14 outip/outqpoutin/outqn data13?ata0 gnd 25 ? 50 ? 25 ? outpoutn figure 8. differential output configuration max5877 14 outip/outqpoutin/outqn data13?ata0 0.1 f av dd1.8 dv dd1.8 0.1 f 0.1 f 0.1 f av dd3.3 dv dd3.3 0.1 f av clk bypassing?ac level *bypass each power-supply pin individually. figure 9. recommended power-supply decoupling andbypassing circuitry downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs ______________________________________________________________________________________ 17 dynamic performance parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog output (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum can be derived from the dac? resolution (n bits): snr db = 6.02 db x n + 1.76 db however, noise sources such as thermal noise, referencenoise, clock jitter, etc., affect the ideal reading; therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first four harmonics, and the dc offset. noise spectral density the dac output noise floor is the sum of the quantiza-tion noise and the output amplifier noise (thermal and shot noise). noise spectral density is the noise power in 1hz bandwidth, specified in dbfs/hz. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre-quency (maximum signal components) to the rms value of their next-largest distortion component. sfdr is usually measured in dbc and with respect to the car- rier frequency amplitude or in dbfs with respect to the dac? full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-/four-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc (or dbfs)of the worst 3rd-order (or higher) imd product(s) to either output tone. adjacent channel leakage power ratio (aclr) commonly used in combination with wideband code-division multiple-access (w-cdma), aclr reflects the leakage power ratio in db between the measured power within a channel relative to its adjacent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. settling time the settling time is the amount of time required from thestart of a transition until the dac output settles its new output value to within the converter? specified accuracy. glitch impulse a glitch is generated when a dac switches betweentwo codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usually specified in pv s. downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs 18 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm downloaded from: http:///
max5877 14-bit, 250msps, high-dynamic-performance, dual dac with lvds inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ___________________ 19 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) revision history pages changed at rev 2: 1, 2, 3, 5, 13, 15, 16, 18 downloaded from: http:///

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